Nowadays many functions usually performed by heavy software algorithms can be executed with dramatically greater performance and simplicity by programmable logic circuits such as PLD's (Programmable Logic Devices) and FPGA's (Field Programmable Gate Arrays). There are examples of acceleration of software algorithms by using programmable logic circuits in several areas such as encrypting and decrypting data, encoding and decoding video signals and other complex mathematic calculations.
The programmable logic circuit building blocks can be as complex as: microprocessors, buffers, multiplexers or converters blocks which can be connected by programming a matrix of connections, determined by a specific configuration file which describes the circuit, usually called “bitstream files”.
In contrast, shared objects (e.g. DLLs) and similar libraries can be dynamically loaded on demand allowing to share objects and interfaces among several different software applications.
The present invention discloses a method for a software application being able to link to specific libraries, shared objects or DLLs which are able to configure on-demand programmable logic circuits and to drive them in a transparent way. Similarly, a shared object can be dynamically loaded and unloaded in memory on demand, and the related circuits in PLD (Programmable Logic Devices) or FPGA (Field Programmable Gate Arrays) can be dynamically allocated and released on demand, optimizing in both cases the resources usage.
A “shared library” or “shared object” is a set of software functions that can be used by different applications running on the same system. It allows the code to be improved without changing the user application and also allows reuse of code among different programs, therefore saving memory resources and loading time. The operating system already provides many shared libraries containing the most common operations and algorithms to be used by installed applications. The system only allocates a shared library if an application requires. When no application requires a given library, it is unloaded, and the related used memory is released.
Some examples of shared objects are: Dynamic-link Library (DLL) for Windows® and Shared Object for Linux.
The patent document U.S. Pat. No. 6,230,307 B1 titled “System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects”, by Xilinx, filed on Jan. 26, 1998, proposes the usage of FPGAs as software using high level atomic blocks in the hardware. The hardware is already programmed with determined types and quantities of those atomic units. The users define the architecture using the resources already available in the hardware as if they are programming software. The present invention differs from document U.S. Pat. No. 6,230,307 B1 for reprogramming the reconfigurable hardware in real time, and making it available on demand, when needed by any application. The OS kernel manages the allocated space and resources inside the hardware and releases or program them when needed without software intervention or even knowledge. By applying the method of the present invention, an application will be able to dynamically link a software library and trigger the hardware functionality as simply as performing a regular application program interface (API) call, accelerating its execution and hiding its complexity.
The patent document US 2005/257186 A1 titled “Operation system for programmable hardware”, by Michael Zilbershlag, filed on May 13, 2004, proposes the usage of FPGA to accelerate the input signals processing from external hardware devices (joysticks, sensors, high speed radios, etc.). The present invention differs from document US 2005/257186 A1 by proposing a broader and more generic method in which any software can be used, regardless of using external hardware for input. The present invention also focuses on the operating system management of the hardware resources and configurations, without necessary intervention in the client application.
The patent document U.S. Pat. No. 9,038,072 B2 titled “System and Method for Hardware-Software Multitasking on a Reconfigurable Computing Platform”, by IMEC, filed on Dec. 10, 2008, proposes the use of a reconfigurable FPGA to accelerate software tasks executing them on hardware, specially focusing on the multitasking of different applications. It is important to state that the application must be specially developed in order to support the proposition. The present invention differs from document U.S. Pat. No. 9,038,072 B2 by including the management of hardware blocks and their functionalities without the intervention in the client application. The client application does not need to be planned nor developed focusing the hardware acceleration, but it can be if necessary. Document U.S. Pat. No. 9,038,072 B2 cannot provide the benefits foreseen by the present invention, in terms of transparency for an external calling application, or in terms of flexibility, and it does not describe a logic link between Shared Object and the programmable hardware. In addition, the present invention includes the management of the allocation/release of circuits, and is not related to multitasking as in document U.S. Pat. No. 9,038,072 B2.
The patent document U.S. Pat. No. 6,557,156 B1 titled “Method of configuring FPGAS for dynamically reconfigurable computing”, by Xilinx Inc., filed on Apr. 10, 2000, proposes a method of configuring FPGAs for reconfigurable computing. It uses high level code language (i.e. Java) and a set of libraries that allows an application to reprogram the FPGA in real time. The present invention differs from document U.S. Pat. No. 6,557,156 B1 by using the kernel to manage the hardware resources and libraries, allowing that simpler applications to use the advantages of hardware acceleration without any additional development efforts. By applying the present invention, an application will be able to dynamically link a software library and trigger the hardware functionality as simply as performing regular API call, accelerating its execution and hiding its complexity.
The patent document U.S. Pat. No. 6,742,173 B2 titled “Communication and control model for field programmable gate arrays and other programmable logic devices”, by Rincon Research Corporation, filed on Jun. 20, 2002, proposes a method of abstraction of a hardware device (FPGA or other hardware platforms) as a digital storage medium for use with computer systems. The functional set of the hardware can be exposed to software without the knowledge of the architecture and physical composition of FPGA hardware. The present invention differs from document U.S. Pat. No. 6,742,173 B2 because this invention allows a software application to abstract and use hardware acceleration as if it were using software libraries, managing the hardware resources allocation and programming in the Operating System layer. Moreover, the present invention does not need to simulate the hardware as a digital storage medium.
The patent document US 2017/0206864 A1, titled “Methods and Apparatus to Provide Extended Graphics Processing Capabilities”, filed on Apr. 1, 2017, by Intel Corporation, involves (a programmable driver interface) sending a display panel parameter to a shared library module, wherein “shared library module includes a first graphics processing capability”. So, it is mainly covering the process for invoking a shared library module and passing it a parameters, which will lately be processed by a GPU. In an analogy with the present invention, it is related to the Shared Object module function call invocation by an Application which is just the trigger that starts the execution of the this DOI mechanism. However, document US 2017/0206864 A1 does not cover important concepts: the flexibility of functions being partially implemented by hardware program and partially by programmable hardware, functions being called transparently by external application without modifications, and the logical link between a Shared Object and Programmable hardware configuration.
Furthermore, the present invention is also related to the following technologies and solutions:
1) Programmable Logic Devices (http://www.mouser.com/applications/programmable-logic/): There are many types of Programmable Logic Devices (PLDs), beginning with simple combinations of digital logic that are integrated on one chip. Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs) are general-purpose semiconductor devices that can be programmed after shipping. They are very design-flexible and user-customizable hardware devices that can implement any logical function that an application-specific integrated circuit could perform, but the ability to update the functionality offers advantages for many applications.
2) A Programmable Logic Array (PLA) (https://en.wikipedia.org/wiki/Programmable_logic_array) is a kind of programmable logic device (PLD) used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND Gates for N input variables and for M outputs from PLA, there should be M OR Gates, each with programmable inputs from all of the AND gates. This layout allows for a large number of logic functions to be synthesized in the sum of products canonical forms.
3) Hardware Description Language (https://en.wikipedia.org/wiki/Hardware_description_language): in electronics, a Hardware Description Language (HDL) is a specialized computer language, similar to C language, used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits. A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit. HDL can be applied in the present invention to describe a digital logic circuit design, as well as the bitstream files used to program PLD's. It is also comprised in the present invention for one to write digital hardware logic in a Hardware Description Language (HDL) or provide the bitstream to program the reconfigurable hardware directly to attend one's application requirements or improve the execution of the code.
4) A Shared library or Shared object (https://en.wikipedia.org/wiki/Library (computing)#Shared_libraries) is a file that is intended to be shared by executable files and further shared object files. Modules used by a program are loaded from individual shared objects into memory at load time or run time, rather than being copied by a linker when it creates a single monolithic executable file for the program. Most modern operating systems can have shared library files of the same format as the executable files.